Semiconductor structures are constantly being down-sized to meet increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits. As such, Fin Field Effect Transistors (FinFETs) need to be ever more densely packaged within the substrate plane defined by the top surface of the silicone substrate in which the FinFETs are embedded within a semiconductor structure. However, such down-sizing provides technical challenges, which are difficult to solve. For example, leakage currents of FinFETs may increase as the channels within the FinFETs become smaller in length. Moreover, it is becoming ever more difficult to increase the overall area (or footprint) along the substrate plane of a semiconductor structure to accommodate larger numbers of FinFETs.
In addition to the need to downsize FinFETs in a semiconductor structure, there is also a growing demand for greater operational functionality. More specifically, there is a growing demand for dual speed operation of such FinFETs, wherein a FinFET can operate at one speed in one mode, and at another faster speed in another mode.
One class of semiconductor devices that would benefit from such dual speed FinFET operation would be Static Random Access Memory (SRAM) cells. SRAM is typically used in personal computers, workstations, routers, peripheral equipment and the like. SRAM cells are often composed of various pull-up and pull-down transistors connected together to form a pair of cross coupled inverters with opposing logic states. The inverters are connected to a pair of pass-gate transistors, which control the flow of data into and out of the SRAM cell during read and write operations.
It is well known that the stability of SRAM cells depends in large part on the speed of the pass-gate transistors relative to the speed of the pull-up and pull-down transistors. It is also well known that for optimum stability, the speed of the pass-gate transistors should be one speed during a read operation and another faster speed during a write operation of the SRAM cell. Such dual speed operating modes can be accomplished with multiple pass-gate transistors connected in parallel, but would also increase cost, complexity and size of each SRAM cell.
Accordingly, there is a need for a FinFET that has a smaller overall footprint for denser packaging. Additionally, there is a need for such a FinFET to have dual speed operating modes for added functionality.